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<title>mtk-20170518/package/firmware/intel-microcode, branch v17.01.5</title>
<subtitle>MTK 20170518 : Mediatek SDK based on OpenWRT Barrier Breaker</subtitle>
<link rel='alternate' type='text/html' href='http://www.chd.sx/cgit/mtk-20170518/'/>
<entry>
<title>intel-microcode: update to 20180312</title>
<updated>2018-04-04T21:09:31+00:00</updated>
<author>
<name>Zoltan HERPAI</name>
<email>wigyori@uid0.hu</email>
</author>
<published>2018-03-20T13:02:20+00:00</published>
<link rel='alternate' type='text/html' href='http://www.chd.sx/cgit/mtk-20170518/commit/?id=ba502a49a7e4b140ef177cc69db91e8e2eb4069e'/>
<id>ba502a49a7e4b140ef177cc69db91e8e2eb4069e</id>
<content type='text'>
- Update microcode for 24 CPU types
- Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation for:
  Sandybridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake,
  Coffee Lake
- Missing production updates:
   - Broadwell-E/EX Xeons (sig 0x406f1)
   - Anniedale/Morefield, Apollo Lake, Avoton, Cherry Trail, Braswell,
     Gemini Lake, Denverton
- New Microcodes:
   - sig 0x00050653, pf_mask 0x97, 2018-01-29, rev 0x1000140
   - sig 0x00050665, pf_mask 0x10, 2018-01-22, rev 0xe000009

Signed-off-by: Zoltan HERPAI &lt;wigyori@uid0.hu&gt;
(cherry picked from commit 3db9d6e57def2912314c7ce0bc0c282f313ed654)
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Update microcode for 24 CPU types
- Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation for:
  Sandybridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake,
  Coffee Lake
- Missing production updates:
   - Broadwell-E/EX Xeons (sig 0x406f1)
   - Anniedale/Morefield, Apollo Lake, Avoton, Cherry Trail, Braswell,
     Gemini Lake, Denverton
- New Microcodes:
   - sig 0x00050653, pf_mask 0x97, 2018-01-29, rev 0x1000140
   - sig 0x00050665, pf_mask 0x10, 2018-01-22, rev 0xe000009

Signed-off-by: Zoltan HERPAI &lt;wigyori@uid0.hu&gt;
(cherry picked from commit 3db9d6e57def2912314c7ce0bc0c282f313ed654)
</pre>
</div>
</content>
</entry>
<entry>
<title>firmware: add microcode package for Intel</title>
<updated>2018-03-04T16:37:15+00:00</updated>
<author>
<name>Zoltan HERPAI</name>
<email>wigyori@uid0.hu</email>
</author>
<published>2018-02-10T20:19:41+00:00</published>
<link rel='alternate' type='text/html' href='http://www.chd.sx/cgit/mtk-20170518/commit/?id=681aaaf719ecae48126ea3be0fe6e150c5ee3b31'/>
<id>681aaaf719ecae48126ea3be0fe6e150c5ee3b31</id>
<content type='text'>
Compiling the Intel microcode package results in a
microcode.bin and a microcode-64.bin. As we can
decide based on the subtarget which should be used,
we'll only split the required .bin file with
iucode-tool.

x64 will get the intel-microcode-64.bin
All other variants will get intel-microcode.bin

The microcodes will be updated from preinit via a common
script - that's the earliest place where we can do it.

Signed-off-by: Zoltan HERPAI &lt;wigyori@uid0.hu&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Compiling the Intel microcode package results in a
microcode.bin and a microcode-64.bin. As we can
decide based on the subtarget which should be used,
we'll only split the required .bin file with
iucode-tool.

x64 will get the intel-microcode-64.bin
All other variants will get intel-microcode.bin

The microcodes will be updated from preinit via a common
script - that's the earliest place where we can do it.

Signed-off-by: Zoltan HERPAI &lt;wigyori@uid0.hu&gt;
</pre>
</div>
</content>
</entry>
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