From dd092fd10cb1b5e4ef5414952ee0180e2e616886 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 20 Nov 2012 07:19:10 +0000 Subject: ramips: set clk_is_20mhz for rt2x00 on RT3352/RT5350 Signed-off-by: Daniel Golle Signed-off-by: Gabor Juhos SVN-Revision: 34270 --- .../linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target/linux/ramips/files/arch/mips/include/asm') diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 949232d..943facb 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -111,6 +111,8 @@ #define RT5350_SYSCFG0_DRAM_SIZE_32M 3 #define RT5350_SYSCFG0_DRAM_SIZE_64M 4 +#define RT3352_SYSCFG0_XTAL_SEL BIT(20) + #define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) #define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) -- cgit v1.1