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| author | Florian Fainelli <florian@openwrt.org> | 2009-08-11 18:50:07 +0000 |
|---|---|---|
| committer | Florian Fainelli <florian@openwrt.org> | 2009-08-11 18:50:07 +0000 |
| commit | dd8b0f9fb9279bd038432a660406ea17c9e2158b (patch) | |
| tree | 5f1bee5a09a734c077015b20113934d321767fd1 /target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h | |
| parent | b520582861140dfbea1ad27e8a8ecf38a4639fc7 (diff) | |
| download | mtk-20170518-dd8b0f9fb9279bd038432a660406ea17c9e2158b.zip mtk-20170518-dd8b0f9fb9279bd038432a660406ea17c9e2158b.tar.gz mtk-20170518-dd8b0f9fb9279bd038432a660406ea17c9e2158b.tar.bz2 | |
more bcm63xx definition fixes, thanks AndyI
SVN-Revision: 17227
Diffstat (limited to 'target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h')
| -rw-r--r-- | target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h index 693989c..e27bd5b 100644 --- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h +++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h @@ -129,10 +129,10 @@ enum bcm63xx_regs_set { #define BCM_6338_UART0_BASE (0xfffe0300) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) -#define BCM_6338_UDC0_BASE (0xdeadbeef) +#define BCM_6338_UDC0_BASE (0xfffe3000) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) -#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) +#define BCM_6338_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) @@ -159,14 +159,14 @@ enum bcm63xx_regs_set { #define BCM_6345_UART0_BASE (0xfffe0300) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) -#define BCM_6345_UDC0_BASE (0xdeadbeef) -#define BCM_6345_USBDMA_BASE (0xfffe2800) +#define BCM_6345_UDC0_BASE (0xfffe2100) +#define BCM_6345_USBDMA_BASE (0xfffe2b00) #define BCM_6345_ENET0_BASE (0xfffe1800) #define BCM_6345_ENETDMA_BASE (0xfffe2800) #define BCM_6345_PCMCIA_BASE (0xfffe2028) #define BCM_6345_MPI_BASE (0xdeadbeef) -#define BCM_6345_OHCI0_BASE (0xfffe2100) -#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) +#define BCM_6345_OHCI0_BASE (0xdeadbeef) +#define BCM_6345_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6345_DSL_BASE (0xdeadbeef) @@ -598,7 +598,7 @@ enum bcm63xx_irq { #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6345_UDC0_IRQ (IRQ_INTERNAL_BASE + 5) #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |