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| author | Felix Fietkau <nbd@openwrt.org> | 2015-07-15 08:17:23 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-07-15 08:17:23 +0000 |
| commit | 2666403c3a850088a440d65f1a49004f1e9d926c (patch) | |
| tree | daf9fd32309fd2492ca71df4839b96ea56cb80eb /target/linux/generic/files/drivers/net/phy/ar8216.h | |
| parent | 52ea491bdf6c57fdd60c5ffc268af3bd67c35103 (diff) | |
| download | mtk-20170518-2666403c3a850088a440d65f1a49004f1e9d926c.zip mtk-20170518-2666403c3a850088a440d65f1a49004f1e9d926c.tar.gz mtk-20170518-2666403c3a850088a440d65f1a49004f1e9d926c.tar.bz2 | |
ar8216: add reading ARL table for AR8216/AR8236/AR8316
Adds the chip-specific part of reading ARL table for AR8216/AR8236/AR8316.
It's based on the AR8236 datasheet and compile-tested only as I couldn't
find datasheets for AR8216/AR8316 and don't own devices with these chips.
The existing ar8216_atu_flush implementation was used for all three
chip types, therefore I guess they share a common ATU register layout.
More testing would be appreciated.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46379
Diffstat (limited to 'target/linux/generic/files/drivers/net/phy/ar8216.h')
| -rw-r--r-- | target/linux/generic/files/drivers/net/phy/ar8216.h | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/target/linux/generic/files/drivers/net/phy/ar8216.h b/target/linux/generic/files/drivers/net/phy/ar8216.h index 0f53f23..934a8b5 100644 --- a/target/linux/generic/files/drivers/net/phy/ar8216.h +++ b/target/linux/generic/files/drivers/net/phy/ar8216.h @@ -79,7 +79,7 @@ #define AR8236_VTUDATA_MEMBER BITS(0, 7) #define AR8216_VTUDATA_VALID BIT(11) -#define AR8216_REG_ATU 0x0050 +#define AR8216_REG_ATU_FUNC0 0x0050 #define AR8216_ATU_OP BITS(0, 3) #define AR8216_ATU_OP_NOOP 0x0 #define AR8216_ATU_OP_FLUSH 0x1 @@ -91,14 +91,31 @@ #define AR8216_ATU_ACTIVE BIT(3) #define AR8216_ATU_PORT_NUM BITS(8, 4) #define AR8216_ATU_FULL_VIO BIT(12) -#define AR8216_ATU_ADDR4 BITS(16, 8) -#define AR8216_ATU_ADDR5 BITS(24, 8) +#define AR8216_ATU_ADDR5 BITS(16, 8) +#define AR8216_ATU_ADDR5_S 16 +#define AR8216_ATU_ADDR4 BITS(24, 8) +#define AR8216_ATU_ADDR4_S 24 -#define AR8216_REG_ATU_DATA 0x0054 +#define AR8216_REG_ATU_FUNC1 0x0054 #define AR8216_ATU_ADDR3 BITS(0, 8) +#define AR8216_ATU_ADDR3_S 0 #define AR8216_ATU_ADDR2 BITS(8, 8) +#define AR8216_ATU_ADDR2_S 8 #define AR8216_ATU_ADDR1 BITS(16, 8) +#define AR8216_ATU_ADDR1_S 16 #define AR8216_ATU_ADDR0 BITS(24, 8) +#define AR8216_ATU_ADDR0_S 24 + +#define AR8216_REG_ATU_FUNC2 0x0058 +#define AR8216_ATU_PORTS BITS(0, 6) +#define AR8216_ATU_PORT0 BIT(0) +#define AR8216_ATU_PORT1 BIT(1) +#define AR8216_ATU_PORT2 BIT(2) +#define AR8216_ATU_PORT3 BIT(3) +#define AR8216_ATU_PORT4 BIT(4) +#define AR8216_ATU_PORT5 BIT(5) +#define AR8216_ATU_STATUS BITS(16, 4) +#define AR8216_ATU_STATUS_S 16 #define AR8216_REG_ATU_CTRL 0x005C #define AR8216_ATU_CTRL_AGE_EN BIT(17) |