diff options
Diffstat (limited to 'target/linux/ramips/patches/121-use-watchdog-for-soft-reset.patch')
| -rwxr-xr-x | target/linux/ramips/patches/121-use-watchdog-for-soft-reset.patch | 132 |
1 files changed, 132 insertions, 0 deletions
diff --git a/target/linux/ramips/patches/121-use-watchdog-for-soft-reset.patch b/target/linux/ramips/patches/121-use-watchdog-for-soft-reset.patch new file mode 100755 index 0000000..54c4d40 --- /dev/null +++ b/target/linux/ramips/patches/121-use-watchdog-for-soft-reset.patch @@ -0,0 +1,132 @@ +Index: linux-3.10.14/arch/mips/ralink/reset.c +=================================================================== +--- linux-3.10.14.orig/arch/mips/ralink/reset.c ++++ linux-3.10.14/arch/mips/ralink/reset.c +@@ -42,6 +42,8 @@ + #include <asm/mach-ralink/generic.h> + #include <linux/pm.h> + #include <linux/delay.h> ++//#include "../../arch/mips/ralink/rt_timer.h" ++#include "rt_timer.h" + + static void mips_machine_restart(char *command); + static void mips_machine_halt(void); +@@ -49,12 +51,118 @@ static void mips_machine_power_off(void) + + static void mips_machine_restart(char *command) + { ++ /* workaround: use watchdog to reset the system. */ ++ unsigned int result; ++ printk("wdg reset\n"); ++#if defined(CONFIG_RALINK_MT7620) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x3<<21); ++ result |= (0x0<<21); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer load */ ++ sysRegWrite(TMR1LOAD, (40000000/65536)); ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#elif defined(CONFIG_RALINK_MT7621) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x3<<8); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer to 100ms */ ++ result=sysRegRead(TMR1CTL); ++ result &= 0x0000FFFF; ++ result |= (1000<<16); // 1us * 1000 = 1ms ++ sysRegWrite(TMR1CTL, result); ++ sysRegWrite(TMR1LOAD, 100); // 1ms * 100 = 100ms ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#elif defined(CONFIG_RALINK_MT7628) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x1<<14); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer to 100ms */ ++ result=sysRegRead(TMR1CTL); ++ result &= 0x0000FFFF; ++ result |= (1000<<16); // 1us * 1000 = 1ms ++ sysRegWrite(TMR1CTL, result); ++ sysRegWrite(TMR1LOAD, 100); // 1ms * 100 = 100ms ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#endif ++ printk("normal reset\n"); + *(volatile unsigned int*)(SOFTRES_REG) = GORESET; + *(volatile unsigned int*)(SOFTRES_REG) = 0; + } + + static void mips_machine_halt(void) + { ++ /* workaround: use watchdog to reset the system. */ ++ unsigned int result; ++ printk("wdg reset\n"); ++#if defined(CONFIG_RALINK_MT7620) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x3<<21); ++ result |= (0x0<<21); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer load */ ++ sysRegWrite(TMR1LOAD, (40000000/65536)); ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#elif defined(CONFIG_RALINK_MT7621) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x3<<8); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer to 100ms */ ++ result=sysRegRead(TMR1CTL); ++ result &= 0x0000FFFF; ++ result |= (1000<<16); // 1us * 1000 = 1ms ++ sysRegWrite(TMR1CTL, result); ++ sysRegWrite(TMR1LOAD, 100); // 1ms * 100 = 100ms ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#elif defined(CONFIG_RALINK_MT7628) ++ #if defined(CONFIG_RALINK_TIMER_WDG_RESET_OUTPUT) ++ /* switch to watchdog mode */ ++ result=sysRegRead(GPIOMODE); ++ result &= ~(0x1<<14); ++ sysRegWrite(GPIOMODE,result); ++ #endif ++ /* set timer to 100ms */ ++ result=sysRegRead(TMR1CTL); ++ result &= 0x0000FFFF; ++ result |= (1000<<16); // 1us * 1000 = 1ms ++ sysRegWrite(TMR1CTL, result); ++ sysRegWrite(TMR1LOAD, 100); // 1ms * 100 = 100ms ++ /* start watchdog timer */ ++ result=sysRegRead(TMR1CTL); ++ result |= (1<<7); ++ sysRegWrite(TMR1CTL,result); ++#endif ++ printk("normal reset\n"); + *(volatile unsigned int*)(SOFTRES_REG) = (0x1)<<26; // PCIERST + mdelay(10); + *(volatile unsigned int*)(SOFTRES_REG) = GORESET; |